A 3D IC package contains two or more integrated circuit dies (ICs) stacked vertically so that they occupy less space. Power and signal communication connections between the vertically stacked ICs may be made using through-semiconductor-vias, also referred to as through-silicon-vias (TSV), which pass through the entire thickness of a die, permitting connections between conductive patterns on the front face and back face of the die. The resulting package has no added length or width.
3D IC packages present new challenges for designers. The area of the chip that is used for TSVs is not available for other devices, reducing the available area for operational devices and spare cells.
If three or more dies are included in the stack, then all of the dies except for the topmost die and bottommost die (i.e., the interior dies) are sandwiched between other dies above and below. Because the semiconductor die materials are generally thermally insulating, heat dissipation presents a challenge in 3D ICs. It is not practical to provide a large heat spreader on the interior dies.